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mi tsub ishi M65580MAP-XXXFP mitsubishi semiconductor < digital ic > digital video/chroma/deflection + mcu preliminary note : this is not a final specification. some of information in this document are subject to changes. description the m65580 ma p- xxx fp are semiconductor integrated circuits designed with c mos silicon gate technology for ntsc television system, include 8bit mcu( m37272ma core) with a closed caption decoder and circuits needed for tv baseband s ignal s( video and chroma) processor and deflection in a chip. pcb area and e mi noise can be redu ced by one chip and 80qfp, and internal conne c tion of osd signals. and it can realize a adjust ment free system by built-in mcu and get a high perfor mance adaptive yc separation by 1 line memory. the above technology make s it s performance more stable and better. feature ? y/ c processor : 8bit input, 10bit output digital pro cessing ? defle c tion processor : optimized system by conventional analog and digital mixed solution ? a dc&d ac : 8bit high speed video adc & 10bit high speed video d ac [mcu block] mcu(single microcomputer ) in this ic ha s almost same function and performance as m37272 ma -xxx sp/fp in mass-production. and it i s operated by si mple in s tru c tion in the sa me memory space as that of built-in ro m , r am , i /o. i t has a osd, data slicer , and i 2 c-b us interface. so it i s very useful for a channel selection system for n tsc t v with a closed caption de coder. [asic block] asic blo ck consists of the following blocks. (1) analog frontend blo ck ; analog s w (2 c vbs(tv&ext) inputs, y /c signals to one signal, 2 channel s 8 bit high speed video adcs, and a cc amplifiers (2) video and chro ma block ; a high perfor mance 2 line adaptive yc separation by 1 line memory, video blo cks including sharpness, yn r, a high performan ce b la ckstretch circuits, chroma decoder, and rgb matrix including osd mixing circuit. (3) defle c tion block ; a high performance sync separation by analog and digital mixed solution (4) analog ba ckend blo ck ; 3 channel s 10 bit high speed video dac s for cutoff & drive, and mute circuit . application ntsc t v with a c lo sed caption decoder 1 pin configur a t ion ( top v ie w) 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 M65580MAP-XXXFP neck protector hvco f/b v-ramp out afc1 filter x-ray protect x-tal chroma apc filter vdd(vcxo) b out vss(output) g out vdd(output) r out vz out tv in vrb p01/pwm1 p02/pwm2 p03/pwm3 p04/pwm4 p05/ad3 p06/int2/ad4 p07/int1 p23/tim3 p24/tim2 p25/ad5 hlf vhold cv in cn vss x in x out p00/pwm0 p50/hsync in/out p51/vsync p52/r p53/out1 p30/g p31/b p10/out2 p11/scl1 p12/scl2 p13/sda1 p14/sda2 scl half tone osd(b) in osd(g) in fast blk osd(r) in v-pulse out vss(def) vdd(def) fbp in h out sda 64 53 54 55 56 57 58 59 60 61 62 63 46 47 48 49 50 51 52 41 42 43 44 45 vss vss(digital) p16/ad2/tim2 p15/ad1/int3/fscin p20/sclk/ad6 p21/sout/ad7 p22/sin/ad8 resetb p26/fscin/xcin p27/xcout vcc filt vdd(input) y sw out sync sep in resetb(asic) clk out vdd(digital) osd clk c in vrt y in vss(input) ext in 1 12 11 10 9 8 7 6 5 4 3 2 19 18 17 16 15 14 13 24 23 22 21 20
mi tsub ishi M65580MAP-XXXFP mitsubishi semiconductor < digital ic > digital video/chroma/deflection + mcu preliminary note : this is not a final specification. some of information in this document are subject to changes. block diagra m (whol e) 2 19 21 25 23 42 41 37 44 43 40 35 34 38 39 33 27 31 vz out 29 vss(output) vdd(output) 36 12 14 16 26 24 22 20 32 30 28 15 x-ray protect vss(digital) vdd(digital) tv in c in y in ext in reset b out g out r out signal processor clk(fsc) out 46 45 sda scl 17 13 sync sep in 18 y sw out clk-2 out 11 48 49 51 50 53 56 58 57 55 59 52 54 47 1 vss vcc 3 77 75 76 60 62 61 osd(b) in osd(g) in osd(r) in fast blk osd h-sync fast blk osd(r) out osd(g) out osd(b) out cv in hlf vhold scl sda p12/scl2 i/o port 63 64 65 66 67 68 69 71 72 73 74 4 7 70 10 9 8 p21/s out/ad7 p20/sclk/ad6 p15/ad1/int3 mcu core m37272ma 78 cnvss 79 80 x in x out 5 fsc in 6 intelligent monitor reset reset half tone half tone osd v-sync osd v-sync 2 filt v-ramp out chroma apc filter xtal neck protector fbp in h out afc1 filter vss(def) vdd(def) vrt vrb vss(input) vdd(input) vdd(vcxo) hvco f/b 3bit digital osd half tone vd hd fast blk intelligent monitor osd half tone vd hd fast blk p14/sda2 p24/tim2 p23/tim3 p07/int1 p06/int2/ad4 p05/ad3 p04/pwm4 p03/pwm3 p02/pwm2 p01/pwm1 p00/pwm0 p22/s in/ad8 p27/xcout p25/ad5 to tv in of asic 2in1 tuner eeprom ccd cvbs/yc input rgb out
mi tsub ishi M65580MAP-XXXFP mitsubishi semiconductor < digital ic > digital video/chroma/deflection + mcu preliminary note : this is not a final specification. some of information in this document are subject to changes. 3 absolute maximum ratings v dd (mcu) pd kt topr tstg supply voltage (mcu) power dissipation thermal derating operating temperature storage temperature v mw 1460 14.6 -20 to 65 -40 to 125 -0.3 to 6.0 ? c ? c symbol parameter ratings unit v dd (asic5v) supply voltage (asic5v) supply voltage (asic3.3v) input voltage (mcu) analog output current -30 v v ma v i (mcu) v o (mcu) i oh (mcu) i ol1 (mcu) i ol2 (mcu) v id (asic) i out (asic) output voltage (mcu) circuit current (mcu) circuit current (p0 0 -p0 7 , p1 0 , p1 5 , p1 6 , p2 0 -p2 7 , p3 0 , p3 1 , p5 2 , p5 3 ) circuit current (p1 1 -p1 4 ) digital input voltage -0.3 to 6.0 -0.3 to 4.0 -0.3 to vcc+0.3 -0.3 to vcc+0.3 v ma ma 0 to 1 (see note 1) ma v v -0.3 to vcc+0.3 all voltage are based on vss.output transistors are cut off. conditions 0 to 2 (see note 2) 0 to 6 (see note 2) v dd (asic3.3v) mw/ ? c recommended operating condition (ta=-20 to 65 ? c , unless otherwise noted) supply voltage (mcu) (see note 3) symbol parameter limits unit v v p5 1 , resetb, x in v v min. typ. max. 4.75 5.0 5.25 v supply voltage (digital) 4.75 5.0 5.25 supply voltage (input) 3.13 3.3 3.47 supply voltage (output) supply voltage (vcxo) 3.13 3.3 3.47 4.75 5.0 5.25 supply voltage (def) v 4.75 5.0 5.25 high input voltage p0 0 -p0 7 , p1 0 -p1 6 , p2 0 -p2 7 , p5 0 , vcc v 0.8vcc high input voltage scl1, scl2, sda1, sda2 (when using i 2 c-bus) vcc v 0.7vcc 0.4vcc v 0 (when using i 2 c-bus) low input voltage scl1, scl2, sda1, sda2 0.3vcc v 0 0.2vcc v 0 1 ma v dd (input) v dd (digital) v dd (mcu) v dd (output) v dd (vcxo) v dd (def) v ih1 (mcu) v ih2 (mcu) v il1 (mcu) low input voltage p0 0 -p0 7 , p1 0 -p1 6 , p2 0 -p2 7 v il2 (mcu) v il3 (mcu) low input voltage (see note 4) p5 0 , p5 1 , resetb, x in , tim2, tim3, int1, int2, int3, s in , s clk high average output current (see note 1) p1 0 -p1 6 , p2 0 -p2 7 , p3 0 , p3 1 , p5 2 , p5 3 i oh (mcu) high input voltage resetb, fbp in, half tone, vcc v 0.8vcc v ih3 (asic) osd(r/g/b) in, fast blk v il4 (asic) low input voltage resetb, fbp in, half tone, 0.2vcc v 0 osd(r/g/b) in, fast blk
mi tsub ishi M65580MAP-XXXFP mitsubishi semiconductor < digital ic > digital video/chroma/deflection + mcu preliminary note : this is not a final specification. some of information in this document are subject to changes. 4 0.88 1.0 0.5 1.5 1.46 2.0 65 75 50 25 0 100 125 150 ambient temperature ta (?c) thermal derating (maximum rating) thermal derating symbol parameter limits unit mhz min. typ. max. oscillation frequency (for cpu operation) x in 7.9 8.0 8.1 input frequency tim2, tim3, int1, int2, int3 100 khz 400 2.5 v 1.5 f(x in ) (mcu) f hs1 (mcu) v i (mcu) input amplitude video signal cv in i ol1 (mcu) 2 ma low average output current (see note 2) p0 0 -p0 7 , p1 0 , p1 5 , p1 6 , p2 0 -p2 7 , p3 0 , p3 1 , p5 2 , p5 3 i ol2 (mcu) low average output current (see note 2) p1 1 -p1 4 6 ma (see note 5) khz oscillation frequency (for sub-clock operation) x cin 29 32 35 f(x cin ) (mcu) mhz oscillation frequency (for osd standard clock) fsc in 3.58 fsc in (mcu) f hs2 (mcu) input frequency s clk mhz 1 input frequency scl1, scl2 khz f hs3 (mcu) 2.0 note 1: the total current that flows out the mcu must be 20ma or less. 2: the total input current to mcu (i ol1 +i ol2 ) must be 30ma or less. 3: use a quartz-crystal oscillator or a ceramic resonator for the cpu oscillation circuit. when using the data slicer, use 8mhz. 4: pin name in each parameter is described pin names. (1) dedicated pins: dedicated pin name. (2) double-/triple-function ports. when the same limits: i/o port name. when the limits of function except ports are different from i/o port limits; function pin name. 5: p0 6 , p0 7 , p1 5 , p2 3 , p2 4 have the hysteresis when these pins are used as interrupt input pins or timer pins. p1 1 -p1 4 have the hysteresis when these pins are used as multi-master i 2 c-bus interface ports. p2 0 -p2 2 have the hysteresis when these pins are used as serial i/o pins. power dissipation pd (w)
mi tsub ishi M65580MAP-XXXFP mitsubishi semiconductor < digital ic > digital video/chroma/deflection + mcu preliminary note : this is not a final specification. some of information in this document are subject to changes. [ mcu block(m37272m a)] description mcu(single microcomputers) in this ic ha s almost same function and performance as m37272 ma -xxx sp/fp in mass- produ c tion. and it is operated by simple instruction in the same memory space as that of built-in ro m , r am , i/o. i t has a osd, data slicer , and i 2 c -b us interface, so it i s very useful for a channel selection system for ntsc t v with a c lo sed caption decoder. features ? nu mber of basic instructions -------- 71 ? memory size ro m -------- 40kbytes ram -------- 1152bytes (ro m correction memory:64bytes included) ? mini mum instruction execution time --------- 0.5 s ( at 8 mh z oscil l ation frequen c y ) ? power source voltage -------- 5v10% ? subroutin e nesting -------- 128 levels( max.) ? interrupts -------- 17bytes 16ve ctor ? 8-bit timers -------- 6 ? progra mm able i /o port s ( ports p0,p1,p2) -------- 23 ? input ports ( ports p50,p51) -------- 2 ? output port s ( ports p30,p31,p52,p53) -------- 4 ? serial i /o -------- 8-bit x 1 channel ? multi- master i 2 c -b us interface -------- 1 ( 2 systems) ? a -d comparator ( 7-bit resolution ) -------- 8 channels ? pw m output c ircuit -------- 8 -bit x 5 ? rom correction function -------- 32 bytes x 2 power dissipation -------- 16 5 mw (at v cc=5.5 v, 8 mh z oscil l ation frequen cy, osd on, and data slicer on) ? clo sed caption data sli cer ? osd function display characters -------- 32 characters x 2 lines(possible to display 3 lines or more by software) kinds of characters 254 kinds chara c ter display area cc mode : 16x26 dots osd mode : 16x20 dots kind s of character sizes cc mode : 1 kind osd mode : 8 kinds kinds of character colors 8 colors(r,g,b) (coloring unit: a character) kinds of background colors cc mode : 1 kind(bla ck) osd mode : 8 kind s ( po ss ible to select color in character unit) display position horizontal : 128 level s vertical : 512 levels a ttribute cc mode : smooth italic, underline, flash, automati c s olid space osd mode : border ( bla ck ) kinds of raster colors 8 kinds smooth roll-up w indow function 5
mi tsub ishi M65580MAP-XXXFP mitsubishi semiconductor < digital ic > digital video/chroma/deflection + mcu preliminary note : this is not a final specification. some of information in this document are subject to changes. description cvbs(tv/ext) signal s or y /c signals input to this ic are converted to 8 bit digital signal by 2 channel s high speed video adcs. these signal s are input to digital section to obtain high perfor mance r/g/b signals. first, cvbs signals are separated to high quality y/c signals by 2 di mensional adaptive yc separation c ircuit, and then y /c signals are converted to r-y&b- y s ignal s by digital ch ro ma decoder, after that, to r/g/b s ignals by rgb matrix circuit. these signals are mixed with osd s ignal s c ome from mcu blo ck, are converted to analog r/g/b signals by 3 channel 10 bit high speed video dac s . in deflection blo ck, to get a better horizontal & vertical signal s , a conventional analog solution by analog c mos technolo gy i s used. asic blo ck consists of the followings blocks. (1) analog frontend blo ck ; analog s w (2 c vbs(tv&ext) inputs, y /c signals to one signal), 2 channel s 8 bit high speed video adcs , and acc amplifiers (2) video and chro ma block ; a high perfor mance 2 line adaptive yc separation by 1 line memory, video blocks including sharpness, yn r, a high performance blackstretch circuits, chroma decoder, and rgb matrix including osd mixing circuit. (3) defle c tion block ; a high performance sync separation by analog and digital mixed solution (4) analog ba ckend blo ck ; 3 channel s 10 bit high speed video dac s for cutoff & drive, and mute circuit. features [video/chro ma block] ? built-in 1 video s w for tv/ext s ignal input ? 2 additional pin s for s(y/c) input ? yuv input s ignal available ( t.b.d ) ? 2 channel 8 bit video a dcs for c vbs(tv&ext) or y/c signal inputs ? built-in adaptive 2 line comb filter(2d ycs) => few dot crawl&crosscolor, and clear color transition ? built-in a high performance blackstretch => dynamic & detailed picture ? digital luminan ce delay circuit => stable y /c timing adjustment ? built-in vcxo circuit(4fsc) ? high resolution r/g/b output => built-in 10bit high speed video d acs ? internal connection of 8 color digital osd ( r/g/b, f.b, h.t ) ? referen ce clk output for tuner (fsc or 4 mh z) ? built-in ynr ( about f sc 1 mh z) ? ga mm a correction(for r/g/b signals) [def le ction block] ? analog( conventional) sync separation => better performance by a b undant experience ? double afc circuit => stable horizontal s canning ? built-in hori zontal referen ce oscil l ator => no ceramic resonator and adju stment free ? h d and vd pul se by countdown => stable hd&vd ? built-in digital vra mp generator [list of main i 2 c bus controllable i tems] ? chip : power-down mode ? analog input stage : cvbs/y&c input sw ? luminan ce processing : sharpness, blackstretch ? chro ma processing : color, tint, killer level ? rgb matrix : acl, osd input level, contrast , brightness ? analog output stage : drive adj.(r/g/b), cutoff adj.(r/g/b) ? defle c tion block : h-pha se, v-size, v -shift, v-linearity [ asic block ] 6
mi tsub ishi M65580MAP-XXXFP mitsubishi semiconductor < digital ic > digital video/chroma/deflection + mcu preliminary note : this is not a final specification. some of information in this document are subject to changes. asic block detailed diagram 7
mi tsub ishi M65580MAP-XXXFP mitsubishi semiconductor < digital ic > digital video/chroma/deflection + mcu preliminary note : this is not a final specification. some of information in this document are subject to changes. function and outline of asic block chip power down mode : 3 modes [ pd0 & pd1 & pd2 ] servi ce sw : stop of verti cal( vra mp) output ( for cutoff adju s tment ) analog block ? input s tage => c vbs&y/c input s ignals input level (cvbs) : 1.23vp-p (173 ire) @max. / 1.0 vp-p @typ. input level (y/c) : y:1.00vp-p (140 ire) @typ./ c:0.7vp-p @typ. ? output stage => rgb output signals output level : 0.7 vp-p (typ.) drive(r&g & b) : -3 to +4 db by 7bit ( white balance) cutoff(r&g&b) : 0.5 v by 9bit (start lighting point) digital block ? 2d ycs adaptive yc separation by u s ing of 1h line memory and original algorithm ? luminan ce processing contrast : 0 to 200 lsb by 7bit brightne ss : -20 to 20 lsb by 8bit (pedestal dc level) sharpne ss : 0 to 3 db by 5bit (by 0, 70, 140, 210ns) delay adjust ment : 0 to 210 n s by 2bit(70ns step) to chroma signal blackstretch : 3 selectable stretch point [ stretch areas ( 0 to 25/30/40 ire ) , through areas ( 25/30/40 ire ~ ) ] 4 selectable black s tretch curves ( 1/4, 2/4, 3/4, 4/4) ? chro ma processing tint : -45 to 45 degree by 7bit => about 0.7 degree : variable de modulator (r- y ) axis (-22.5 to +22.5 degree by 6bit => about 0.7 degree) color : 0 to 200 % by 7bit ? rgb matrix : matrix(r-y s ignal) ratio sele c table (12/8, 13/8, 14/8) acl : auto matic contrast limiter by mcu port(adc) and i 2 c bus ext/rgb : c lip to 7lsb @ data < 0fh blueback : on/off selectable mute : on/off of r/g/b output ne ck protector : r/g/b output to zero( no signal) deflection block ? hori zontal output afc2 phase : +5 to -5 s by 5bit hold => shut down : fh@hold-down : in about 16.5kh z => fh@shutdown : h -stop afc1 gain : nor mal/high selectable for vtr skew ? verti cal output v po s ition : 0 to 16 h by 3 bit => 2h unit(connected with blk) v s ize : 1.4 to 2.6 v by 7bit linearity : 0 to 30 % by 7bit 8
mi tsub ishi M65580MAP-XXXFP mitsubishi semiconductor < digital ic > digital video/chroma/deflection + mcu preliminary note : this is not a final specification. some of information in this document are subject to changes. application e xam pl es 0.1u video det out (1.23vp-p) 0.1u 0.1u 0.1u 0.1u 1m 560 0.1 u 2k +200v fbt acl in 0.1u - dy to h drive 0.1u h-pul s e out sda scl 10k 10k ext in (1.23vp-p) y in (1.00vp-p) c in (0.70vp-p) fbp in 1.5k 1.5k 1.5k reset 5 10 15 74 80 12 11 13 14 76 77 78 79 2 3 4 6 7 8 9 19 18 17 16 1 20 24 23 22 21 65 69 65 66 67 68 70 71 72 73 64 25 29 28 27 26 30 35 36 34 33 32 31 40 39 38 37 39 40 45 49 54 59 53 52 51 41 42 43 44 46 47 48 50 55 56 57 58 60 61 62 63 clk-2 out clk(fsc) out vdd(dig) vss(dig) sync sep. in cvbs(x2) out vdd(input) tv in mcu analog block asic reset in p22/sin/ad8 p21/sout/ad7 p20/sclk/ad6 p15/ad1/int3 reset in p26/fscin p27/xcout vcc vss(input) ext in vrt vss filt digital block p16/ad2/tim2 (int. mon. in/out) r(osd) in f.b in sda scl g(osd) in b(osd) in p51/vsync vdd(def) vss(def.) p52/rout p53/out1 p30/gout p31/bout vd out p10/out2 p11/scl1 p12/scl2 p13/sda1 p14/sda2 h.t in p50/hsync in/out h out p00/pwm0 yin fbp in neck pro 65 64 74 75 5v 5v 3.3v 5v fbt reg 3.3v reg 5v reg 9v 3.3v sw reg reg 5v 150v power on h 15p 15p 470p 0.1 u 0.1u 470p 0.01u 470p 0.1u 0.01u 9
mi tsub ishi M65580MAP-XXXFP mitsubishi semiconductor < digital ic > digital video/chroma/deflection + mcu preliminary note : this is not a final specification. some of information in this document are subject to changes. 10 electrical characteristics icc standard conditions icc50 5.0v supply current - - 3,14, 33,42 102 116 130 ma supply of mcu, digital, vcxo and deflection icc33 3.3v supply current - - 18, 29 47 56 65 ma supply of a/d and d/a video standard conditions of video character - - - - - - - 2agtv video sw output level (tv input) 26 sg.a 18 1.5 1.7 1.9 v pp 2agev video sw output level (external input) 20 sg.a 18 1.5 1.7 1.9 v pp vtyp video standard output 26 sg.a 28,30, 32 590 740 890 mv pp fby video frequency characteristics 26 sg.b 28,30, 32 -3 0 3 db f=5mhz y/c1 y/c separation function 1 26 sg.e 28,30, 32 - -30 -20 db feb=fec=fsc y/c2 y/c separation function 2 26 sg.e 28,30, 32 -3 0 3 db feb=fsc, fec=fsc 1/2f h y/c3 y/c separation function 3 26 sg.e 28,30, 32 - -30 -20 db feb=fsc, fec=fsc f h ydl0 y total delay time 26 sg.a 28,30, 32 2.4 3.0 3.6 sec ydl1 y delay time 1 26 sg.a 28,30, 32 50 70 90 nsec ydl1=measure ydl0 ydl2 y delay time 2 26 sg.a 28,30, 32 50 70 90 nsec ydl2=measure ydl1 ydl3 y delay time 3 26 sg.a 28,30, 32 50 70 90 nsec ydl3=measure ydl2 gtnor video tone control characteristic 1 26 sg.b 28,30, 32 640 800 960 mv f=2.5mhz gtmax video tone control characteristic 2 26 sg.b 28,30, 32 1 2.5 4 db f=2.5mhz gtmin video tone control characteristic 3 26 sg.b 28,30, 32 -7 -4 -1 db f=2.5mhz bls black stretch characteristic 26 sg.d 28,30, 32 20 50 80 mv vy=0.18v, 45h=80h(bls on) / 00h(bls off) ht half tone function 26 sg.a 28,30, 32 -9 -6 -3 db symbol parameter input signal pins sg test point limits min. max. typ. unit r e marks ( ta = 25 o c , vd d = 5. 0 v , 3.3 v )
mi tsub ishi M65580MAP-XXXFP mitsubishi semiconductor < digital ic > digital video/chroma/deflection + mcu preliminary note : this is not a final specification. some of information in this document are subject to changes. 1 1 standard condition of chroma parameter - - - - - - - 5dh=03h chroma standard output (r-y) 26 sg.e 28 155 180 205 mv f eb =f ec +50khz chroma standard output (b-y) 26 sg.e 32 275 310 345 mv acc characteristic 1 26 sg.e 28 -3 0 3 db v eb , v ec : +6db of typical input level acc characteristic 2 26 sg.e 28 -3 0 3 db killer operation input level 26 sg.e 28 -40 -35 -30 db color residual at killer on 26 sg.e 28 - -40 -28 db apc pull-in range (upper) 26 sg.e 28 400 - - hz apc pull-in range (lower) 26 sg.e 28 - - -400 hz demodulated output ratio 26 sg.e 28,32 0.47 0.57 0.67 - demodulation phase angle 26 sg.f 28,32 85 90 95 deg color control characteristic 1 26 sg.e 28 160 200 240 % color control characteristic 2 26 sg.e 28 - 0 10 % tint control characteristic 1 26 sg.f 28,32 30 45 60 deg tint control characteristic 2 26 sg.f 28,32 -60 -45 -30 deg clk output frequency 26 sg.c 15 3.578 3.579 3.580 mhz clk output amplitude 26 sg.c 15 350 500 650 mv pp cnorb acc1 apcl demr vikn apcu acc2 killp vclk tc2 fclk ccon 2 tc1 demp ccon 1 cnorr f eb =f ec +50khz v eb , v ec : -20db of typical input level v eb , v ec : variable f eb =f ec : variable f eb =f ec +50khz f eb =f ec : variable v eb = 0mv f eb =f ec +50khz f eb =f ec +50khz symbol test point sg pins input signal parameter limits min. typ. max. unit remarks chroma
mi tsub ishi M65580MAP-XXXFP mitsubishi semiconductor < digital ic > digital video/chroma/deflection + mcu preliminary note : this is not a final specification. some of information in this document are subject to changes. 1 2 limits min. typ. max. rgb standard condition of rgb parameter - - - - - - - vped output pedestal voltage 26 sg.d 28,30, 32 2.7 3.0 3.3 v v y = 0.0v mtxrb matrix ratio r/b 26 sg.h 28,32 0.74 0.92 1.10 - mtxgb matrix ratio g/b 26 sg.h 30,32 0.24 0.33 0.42 - gymax contrast control characteristic 1 26 sg.d 28,30, 32 160 200 240 % vy =0.286v gymin contrast control characteristic 2 26 sg.d 28,30, 32 - 0 10 % vy =0.286v gyeclip contrast control characteristic 5 48,49, 51 sg.g 28,30, 32 250 300 350 mv lum max brightness control characteristic 2 26 sg.d 28,30, 32 100 150 200 mv lum min brightness control characteristic 3 26 sg.d 28,30, 32 -200 -150 -100 mv vy =0.286v d(r)1 r drive control characteristic 1 26 sg.d 28 1.5 3.5 5.5 db vy =0.286v d(g)1 g drive control characteristic 1 26 sg.d 30 1.5 3.5 5.5 db vy =0.286v d(b)1 b drive control characteristic 1 26 sg.d 32 1.5 3.5 5.5 db vy =0.286v d(r)2 r drive control characteristic 2 26 sg.d 28 -4.6 -2.6 -0.6 db vy =0.286v d(g)2 g drive control characteristic 2 26 sg.d 30 -4.6 -2.6 -0.6 db vy =0.286v d(b)2 b drive control characteristic 2 26 sg.d 32 -4.6 -2.6 -0.6 db vy =0.286v c(r)1 r cut off control characteristic 1 26 sg.d 28 210 260 310 mv vy =0.286v c(g)1 g cut off control characteristic 1 26 sg.d 30 210 260 310 mv vy =0.286v c(b)1 b cut off control characteristic 1 26 sg.d 32 210 260 310 mv vy =0.286v c(r)2 r cut off control characteristic 2 26 sg.d 28 -310 -260 -210 mv vy =0.286v c(g)2 g cut off control characteristic 2 26 sg.d 30 -310 -260 -210 mv vy =0.286v c(b)2 b cut off control characteristic 2 26 sg.d 32 -310 -260 -210 mv vy =0.286v osd(r) osd (r) output level 51 sg.g 28 500 600 700 mv pp osd(g) osd (g) output level 49 sg.g 30 500 600 700 mv pp osd(b) osd (b) output level 48 sg.g 32 500 600 700 mv pp sosd1 osd speed characteristic 1 48,49, 51 sg.g 28,30, 32 - 100 200 nsec sosd2 osd speed characteristic 2 48,49, 51 sg.g 28,30, 32 - 100 200 nsec off(r) offset voltage between r and osd(r) - - - -50 0 50 mv difference at pedestal level off(g) offset voltage between g and osd(g) - - - -50 0 50 mv difference at pedestal level off(b) offset voltage between b and osd(b) - - - -50 0 50 mv difference at pedestal level neck neck protector function threshold voltage 26 sg.a 40 1.0 1.3 1.6 v while monitoring at pins 28, 30, 32 symbol test point sg pins input signal parameter remarks unit
mi tsub ishi M65580MAP-XXXFP mitsubishi semiconductor < digital ic > digital video/chroma/deflection + mcu preliminary note : this is not a final specification. some of information in this document are subject to changes. 1 3 def standard condition of defrection parameter - - - - - - - fh1 horizontal free-running frequency 1 - - 44 15.53 15.73 15.93 khz fh2 horizontal free-running frequency 2 - - 44 13.72 14.32 14.92 khz fh3 horizontal free-running frequency 3 - - 44 17.25 17.85 18.45 khz fphu horizontal pull-in range (upper) 17 sg.i 44 250 500 - hz vary frequency of input signal. fphl horizontal pull-in range (lower) 17 sg.i 44 - -500 -250 hz vary frequency of input signal. hpv horizontal pulse amplitude 26 sg.a 44 4.0 4.5 5.0 v hptw horizontal pulse width 26 sg.a 44 19.3 22.3 25.3 sec hpd horizontal pulse duty cycle 26 sg.a 44 30 35 40 % hpt1 horizontal pulse timing 1 26 sg.a 44 8.7 10.7 12.7 sec hpt2 horizontal pulse timing 2 26 sg.a 44 2.2 4.2 6.2 sec hpt3 horizontal pulse timing variable range 26 sg.a 44 4.5 6.5 8.5 sec hpt2 hpt1 hdown hold down function threshold voltage 26 sg.a 36 3.0 3.1 3.2 v while monitoring at pin 44 sdown shut down function threshold voltage 26 sg.a 36 3.3 3.5 3.7 v while monitoring at pin 44 fv vertical free-running frequency - - 38 55 60 65 hz svc service mode function - - 38 2.5 2.8 3.1 v fpvu vertical pull-in frequency (upper) 17 sg.j 38 - - 63 hz vary frequency of input signal. fpvl vertical pull-in frequency (lower) 17 sg.j 38 57 - - hz vary frequency of input signal. vrsi 1 vertical ramp size 26 sg.a 38 2.1 2.5 2.9 v pp vrsc 1 vertical ramp size control range 1 26 sg.a 38 20 27 35 % vrsc 2 vertical ramp size control range 2 26 sg.a 38 -35 -27 -20 % vlin 1 vertical ramp linearity control range 1 26 sg.a 38 -5 0 5 % vlin 2 vertical ramp linearity control range 2 26 sg.a 38 19 24 29 % vrpo 1 vertical ramp position control range 1 26 sg.a 38 0 50 200 sec vrpo 2 vertical ramp position control range 2 26 sg.a 38 790 940 1090 sec (measured value) (vrpo 1) vw vertical pulse width 26 sg.a 52 0.35 0.53 0.65 msec vblkw vertical blanking width 26 sg.a 28,30, 32 1.52 1.64 1.76 msec wvss minimum vertical sync detection width 26 sg.a 11 13 18 23 sec symbol parameter input signal sg pins test point max. typ. min. limits remarks unit
mi tsub ishi M65580MAP-XXXFP mitsubishi semiconductor < digital ic > digital video/chroma/deflection + mcu preliminary note : this is not a final specification. some of information in this document are subject to changes. 1 4 electrical characteristics (mcu part) (vcc=5v10%, vss = 0v, f(x in )=8mhz, ta=20?c to 65?c, unless otherwise noted) max. 30 45 200 4 100 10 0.4 0.4 0.6 5 5 high output voltage low output voltage low output voltage p 1 1 p1 4 hysteresis (see note 1) low input leak current i 2 c-bus bus switch connection resistor (between scl1 and scl2, sda1 and sda2) symbol parameter t est conditions w ait mode system operation power source current t est circuit 1 min. 2.4 limits t yp. 15 30 2 25 1 0.5 2 3 4 5 4 unit ma ma v v v a a a high input leak current p0 0 p0 7 , p1 0 p1 6 , p2 0 p2 7 , p5 0 , p5 1 , reset reset, p5 0 p5 1 , int1, int2, int3, tim2, tim3, s in , s clk , scl1, scl2, sda1, sda2 p0 0 p0 7 , p1 0 p1 6 , p2 0 p2 7 , p5 0 , p5 1 , reset p0 0 p0 7 , p1 0 , p1 5 , p1 6 , p2 0 p2 7 , p3 0 , p3 1 , p5 2 , p5 3 p1 0 p1 6 , p2 0 p2 7 , p3 0 , p3 1 , p5 2 , p5 3 a v cc = 5.5 v, f(x in ) = 0, f(x cin ) = 32 khz, osd off, data slicer off, low-power dissipation mode set (cm5 = "0", cm6 = "1") v cc = 5.5 v, f(x in ) = 0, f(x cin ) = 32 khz, low-power dissipation mode set (cm5 = "0", cm6 = "1") v cc = 5.5 v, f(x in ) = 0, f(x cin ) = 0 v cc = 5.5 v, f(x in ) = 8 mhz v cc = 5.5 v, f(x in ) = 8 mhz osd off data slicer off osd on v cc = 4.5 v i oh = 0.5 ma v cc = 4.5 v i ol = 0.5 ma v cc = 5.0 v i ol = 3 ma i ol = 6 ma v cc = 4.5 v v cc = 4.5 v v cc = 5.5 v v i = 5.5 v v cc = 5.5 v v i = 0 v i cc v oh v ol i izh i izl v t+ v t r bs notes 1: p0 6 , p0 7 , p1 5 , p2 3 , p2 4 have the hysteresis when these pins are used as interrupt input pins or timer input pins. p1 1 p1 4 have the hysteresis when these pins are used as multi-master i 2 c-bus interface ports. p2 0 p2 2 have the hysteresis when these pins are used as serial i/o pins. 2: connect 0.1f or more capacitor externally between the power source pins v cc v ss so as to reduce power source noise. also connect 0.1f or more capacitor externally between the pins v cc cnv ss . 3: use a quartz-crystal oscillator or a ceramic resonator for the cpu oscillation circuit. when using the data slicer, use 8 mhz. 4: pin names in each parameter is described as bellow. 130 1.3 60 (1) dedicated pin: dedicated pin names. (2) double-/triple-function ports when the same limits: i/o port name. when the limits of functions except ports are different from i/o port limits: function pin name.
mi tsub ishi M65580MAP-XXXFP mitsubishi semiconductor < digital ic > digital video/chroma/deflection + mcu preliminary note : this is not a final specification. some of information in this document are subject to changes. 1 5 a6 a5 a4 a3 a2 a1 a0 r/w 1 0 1 1 1 0 1 1/0 data hex bin d7 d6 d5 d4 d3 d2 d1 d0 initial h stop 00h 00000000 0 0 0 0 0 0 1 0 02h x-ray enable yuv input y/c input ext input tv input y/c through 01h 00000001 0 0 0 0 1 0 0 0 08h ped clamp 02h 00000010 0 0 0 0 1 0 0 0 08h shrapness gain (front) 04h 00000100 v1 v0 v1 v0 v0 v0 v0 v0 a0h shrapness gain (rear) 05h 00000101 v1 v0 v1 v0 v0 v0 v0 v0 a0h (not asigned) ynr sw 06h 00000110 v0 v0 v0 v0 v0 v0 v0 v0 00h 07h 00000111 v0 v0 v0 v1 v0 v1 v0 v1 15h (not asigned) tint control 08h 00001000 v0 v0 v1 v0 v1 v0 v0 v1 29h (not asigned) color control 09h 00001001 v0 v0 v1 v0 v1 v0 v0 v0 28h (not asigned) contrast control 0ah 00001010 v0 v0 v1 v1 v1 v0 v1 v1 3bh 0bh 00001011 v0 v0 v0 v1 v1 v1 v1 v0 1eh 0ch 00001100 v1 v0 v0 v1 v1 v1 v1 v0 5eh 0dh 00001101 v0 v0 v0 v1 v1 v1 v1 v0 0eh 0eh 00001110 v1 v0 v0 v0 v0 v0 v0 v0 80h (not asigned) h free afc1 gain 0fh 00001111 0 0 0 0 1 0 0 0 08h (for evaluation) 2d y/c 10h 00010000 0 0 0 0 0 0 0 0 00h (not asigned) black stre. sw 11h 00010001 v0 v1 v0 v0 v0 v0 v0 v0 40h rgb mute 12h 00010010 1 0 0 0 0 0 0 0 80h service sw 13h 00010011 0 0 0 1 0 0 0 0 10h v-blanking stop 14h 00010100 0 1 0 0 0 0 0 0 40h v-ramp invert 15h 00010101 1 1 1 1 1 1 1 1 ffh 16h 00010110 00h cutoff(r) msb 17h 00010111 00h 18h 00011000 00h cutoff(g) msb 19h 00011001 00h 1ah 00011010 00h cutoff(b) msb 1bh 00011011 00h 1ch 00011100 0 0 0 0 0 0 0 0 00h i/m(d) enable 1dh 00011101 0 0 0 0 0 0 0 0 00h 01010001 0 0 0 0 0 0 0 0 00h note: v0 / v1 ==> v- latch bit d7 d6 d5 d4 d3 d2 d1 d0 60h 01100000 killer h coinci v coinci b_w i i c_still mv_180 det nz k_moni 61h 01100001 62h 01100010 b2 rom msb 63h 01100011 sub address sub address (for evaluation) (for evaluation) hold down level (not asigned) intelligent monitor (analog) (not asigned) intelligent monitor (digital) h vco adjust b2 rom (not asigned) c gain (not asigned) blkdetv gamma control (inhibited) v-ramp linearity v-ramp size v-shift drive (b) cut off (b) cut off (r) drive (r) cut off (g) drive (g) h phase control (not asigned) rgb matrix ratio osd level (g) osd comp osd level (b) brightness control (not asigned) sharpness limitter level half tone osd level (r) sharpness delay (rear) sharpness delay (front) y dl time adj. ynr limitter level power down mode (not asigned) (for evaluation) sync-tip clamp vrt voltage (not asigned) i 2 c bus table slave address= bah(write), bbh(read) write table(input bytes) read table(output bytes) 51h (inhibited) v0 v0 v0 v0 v0 v0 v0 v0 v0 v0 v0 v0 v0 v0 v0 v0 v0 v0 v0 v0 v0 v0 v0 v0 v0 v0 v0 v0 v0 v0 v0 v0 v0 v0 v0 v0 v0 v0 v0 v0 v0 v0 v0 v0 v0 v0 v0 v0
mi tsub ishi M65580MAP-XXXFP mitsubishi semiconductor < digital ic > digital video/chroma/deflection + mcu preliminary note : this is not a final specification. some of information in this document are subject to changes. 1 6 bus function write function bit sub add data discription initial note h stop 1 00h d0 horizontal output switch (0: h out, 1: h stop) 0 power down 2 00h d1-d2 power down mode control (0: normal, 1: pd0, 2: pd1, 3: pd2) 01 input video sw 4 01h d3-d6 video sw selector (1: tv, 2: ext, 4: y/c input, 9: yuv input) 0001 x-ray enable 1 01h d7 x-ray protect function switch (0: x-ray protect off, 1: x-ray protect on) 0 y/c through 1 01h d2 y/c separation input switch (0: y/c sep on, 1: y/c sep. through) 0 sync-tip clamp 3 02h d0-d2 sync-tip clamp switch (0: clamp on, 1: tv clamp off, 2: ext clamp off, 4: y clamp off) 000 ped clamp 1 02h d7 pedestal clamp switch (0: pedestal clamp off, 1: pedestal clamp on) 0 vrt voltage 2 02h d3-d4 reference voltage adjustment for a/d 01 sharpness gain (front) 6 04h d0-d5 over-shoot gain control by 6bit 100000 v latch sharpness delay (front) 2 04h d6-d7 over-shoot width control (0: 0ns, 1: 70ns, 2: 140ns 3: 210ns) 10 v latch sharpness gain (rear) 6 05h d0-d5 pre-shoot gain control by 6bit 100000 v latch sharpness delay (rear) 2 05h d6-d7 pre-shoot width control (0: 0ns, 1: 70ns, 2: 140ns 3: 210ns) 10 v latch ynr sw 7 06h d4 ynr control switch (0: ynr off, 1: ynr on) 0 v latch ynr limiter level 1 06h d0-d3 ynr limiter level control 0000 v latch y dl time adj. 2 06h d5-d6 delay time adjustment of luminance signal (0: 0ns, 1: 70ns, 2: 140ns 3: 210ns) 00 v latch sharpness limiter level 6 07h d0-d5 maximum level control of sharpness 010101 v latch tint control 7 08h d0-d6 tint control by 7bit 0101001 v latch color control 7 09h d0-d6 color saturation control by 7bit 0101000 v latch contrast control 7 0ah d0-d6 contrast control by 7bit 0111011 v latch osd level (r) 6 0bh d0-d5 digital osd (r) level adjustment by 6bit 011110 v latch half tone 2 0bh d6-d7 setting of half tone mode 00 v latch osd level (g) 6 0ch d0-d5 digital osd (g) level adjustment by 6bit 011110 v latch rgb matrix ratio 2 0ch d6-d7 rgb matrix ratio control 10 v latch osd level (b) 6 0dh d0-d5 digital osd (b) level adjustment by 6bit 011110 v latch osd comp 2 0dh d6-d7 digital osd threshold voltage control of input signal 00 v latch brightness control 8 0eh d0-d7 brightness control by 8bit 10000000 v latch afc2 h phase 5 0fh d0-d4 horizontal phase adjustment by 5bit 01000 afc1 gain 1 0fh d5 horizontal afc gain switch (0: low, 1: high) 0 h-free 1 0fh d6 horizontal forced free-running mode switch (0: off, 1: forced free-running) 0 2d y/c 1 10h d4 y/c separation mode switch (0: y/c sep on, 1: y/c sep. through) 0 black stretch sw 1 11h d6 black stretch function on/off switch (0: off, 1: on) 0 gamma control 1 12h d0-d3 rgb gamma threshold control (0:gamma off) 0000 rgb mute 1 12h d7 rgb signal mute on/off switch (0: mute 1: rgb output) 1 hold down level 3 13h d0-d2 hold down level adjustment by 3bit 000 v shift 3 13h d4-d6 v ramp start timing adjustment 2line/step 001 service sw 1 13h d3 service mode switch (0: vertical output on, 1: vertical output off) 0 v-ramp size 7 14h d0-d6 v-ramp amplitude adjustment by 7bit 1000000 test 1 14h d7 no use for customer (test mode) 0 v-ramp linearity 7 15h d0-d6 v-ramp linearity adjustment by 7bit 1111111 v-ramp invert 1 15h d7 v-ramp polarity switch 1 cut off(r) 9 16h d0-d7 r out pedestal level adjustment by 9bit 00000000 17h d7 0 drive(r) 7 17h d0-d6 r out amplitude adjustment by 7bit 0000000 cut off(g) 9 18h d0-d7 g out pedestal level adjustment by 9bit 00000000 19h d7 0 drive(g) 7 19h d0-d6 g out amplitude adjustment by 7bit 0000000 cut off(b) 9 1ah d0-d7 b out pedestal level adjustment by 9bit 00000000 1bh d7 0 drive(b) 7 1bh d0-d6 b out amplitude adjustment by 7bit 0000000 intelligent monitor (analog) 4 1ch d0-d3 intelligent monitor (analog) mode selector 0000 intelligent monitor (digital) 5 1dh d0-d4 intelligent monitor (digital) mode selector 00000 intelligent monitor(d) enable 1 1dh d5 intelligent monitor (digital) function switch (0: off, 1: on) 0 h vco adj. 8 51h d0-d7 h vco free-running frequency adjustment by 8bit 00000000 read k_moni 1 60h d0 color/killer condition (1: color output, 0: killer (color off) ) det_nz 1 60h d1 noise killer det. output (1: noise killer on) mv_180 1 60h d2 reversed burst signal (all reversed) det. output (1: reversed burst) iic_still 1 60h d3 vcr still mode det. output (1: still mode) b_w 1 60h d4 pll killer (chroma) det. output (1: pll killer on) v coinci 1 60h d5 vertical coincidence det. output (1: v coincident) h coinci 1 60h d6 horizontal coincidence det. output (1: h coincident) killer 1 60h d7 c-processor killer det. output (1: c-pro killer on) b2rom 9 61h d0-d7 b2rom output 62h d7 c gain 2 62h d0-d1 acc amplifier status blkdetv 4 63h d4-d7 black det. output of black stretch circuit v latch v latch v latch v latch v latch v latch
mi tsub ishi M65580MAP-XXXFP mitsubishi semiconductor < digital ic > digital video/chroma/deflection + mcu preliminary note : this is not a final specification. some of information in this document are subject to changes. 1 7 m65580map i 2 c bus standard data sub address data sub address data sub address data 00h 00 30h 20 50h 00 01h 08 31h 05 51h 00 02h 08 32h 04 52h 00 03h 21 33h 81 53h 35 04h c0 34h 8d 54h 22 05h c0 35h 63 55h 94 06h 00 36h 79 56h 14 07h 15 37h 50 57h a6 08h 40 38h 55 58h 00 09h 40 39h 25 59h a6 0ah 40 3ah 21 5ah 00 0bh 1e 3bh 19 5bh 00 0ch 9e 3ch b3 5ch 00 0dh 1e 3dh 0f 5dh 80 0eh 80 3eh 06 0fh 10 3fh 08 10h 10 40h 00 11h 4a 41h 01 12h 8d 42h c0 13h 00 43h 04 14h 40 44h 64 15h 40 45h 3d 16h 00 46h 15 17h c0 47h 00 18h 00 48h 83 19h c0 49h 00 1ah 00 4ah a0 1bh c0 4bh 00 1ch 00 4ch 15 1dh 00 4dh 01 4eh 6e 4fh 38
mi tsub ishi M65580MAP-XXXFP mitsubishi semiconductor < digital ic > digital video/chroma/deflection + mcu preliminary note : this is not a final specification. some of information in this document are subject to changes. 1 8 pin no. peripheral circuit of pins description of pin vss (mcu) 1 0v power source for mcu. y 2 filt 2 vcc (mcu) 3 5.0v 5% power source for mcu. p2 7 /xcout 7 4 4 5 p2 6 /fscin/ xcin 5 name note
mi tsub ishi M65580MAP-XXXFP mitsubishi semiconductor < digital ic > digital video/chroma/deflection + mcu preliminary note : this is not a final specification. some of information in this document are subject to changes. 1 9 pin no. peripheral circuit of pins y 6 y c a resetb 6 v ol = 0v : reset state v oh = 5v : release from reset state cmos input impedance>100k p2 2 /sin/ad8 7 p2 1 /sout/ad8 8 p2 0 /sclk/ad6 9 10 p1 6 /ad2/tim2 11 cmos in/out 1 impedance>100k (input) impedance 250 (output) intelligent monitor output (analog/digital) c a 11 y cmos in/out 1 impedance>100k (input) impedance 250 (output) vss (digital) 12 0v p1 5 /ad1/ int3/fscin name note
mi tsub ishi M65580MAP-XXXFP mitsubishi semiconductor < digital ic > digital video/chroma/deflection + mcu preliminary note : this is not a final specification. some of information in this document are subject to changes. 20 pin no. peripheral circuit of pins osd clk y c a 13 13 cmos in/out 1 impedance>100k (input) impedance<100 (output) vdd (digital) 14 impedance 400 esd protect clk out 15 15 reset 16 y c.sync in 17 sync sep. input impedance=n.a. esd protect cmos input impedance>100k 16 17 v il = 0v : reset state v ih = 5v : release from reset state 5.0v 5% power source for digital block. dc 2.5v name note
mi tsub ishi M65580MAP-XXXFP mitsubishi semiconductor < digital ic > digital video/chroma/deflection + mcu preliminary note : this is not a final specification. some of information in this document are subject to changes. 21 pin no. peripheral circuit of pins cvbs out 18 impedance 150 18 3.3v 5% vdd (input) 19 power source for a/d etc. impedance=n.a. ext(cvbs) in 22 20 0v vss (input) 21 power source for a/d etc. tv(cvbs) in 20 22 y in 26 26 vrt 23 vrb 25 impedance>50 23 25 impedance 7.5k c in 24 24 dc : 0.55v (sync) ac : 1.75v p-p (typ.) dc : 1.7v (vrt) 0.5v (vrb) dc : 1.0v ac : 0.286v p-p (burst) dc : 0.5v (sync) ac : 1.0v p-p (typ.) name note
mi tsub ishi M65580MAP-XXXFP mitsubishi semiconductor < digital ic > digital video/chroma/deflection + mcu preliminary note : this is not a final specification. some of information in this document are subject to changes. 22 pin no. peripheral circuit of pins impedance 400 27 vz out 27 impedance 1k 28 30 32 3.3v 5% vdd (output) 29 power source for d/a etc. g out 30 r out 28 b out 32 0v vss (output) 31 power source for d/a etc. apc filter 34 5.0v 5% vdd (vcxo) 33 power source for vcxo etc. 34 impedance=n.a. (additional filter on pcb board) dc : 2.05v dc : 3v (blanking) dc 2.9v name note
mi tsub ishi M65580MAP-XXXFP mitsubishi semiconductor < digital ic > digital video/chroma/deflection + mcu preliminary note : this is not a final specification. some of information in this document are subject to changes. 23 pin no. peripheral circuit of pins impedance 1k x'tal 35 35 impedance>100k x-ray protector 36 esd protect 36 37 afc1 filter 37 impedance 400 v ramp out 38 38 2.5v p-p (typ.) impedance 5k 40 neck protector 40 39 39 hvco f/b impedance=n.a. (additional filter on pcb board) dc 3.0v impedance=n.a. (additional filter on pcb board) dc 2.5v 0.0-3.0 : normal 3.2-3.3 : hold down 3.7-5.0 : shut down 0.0-1.0 : rgb off 1.6-3.0 : normal 4.0-5.0 : test mode name note
mi tsub ishi M65580MAP-XXXFP mitsubishi semiconductor < digital ic > digital video/chroma/deflection + mcu preliminary note : this is not a final specification. some of information in this document are subject to changes. 2 4 pin no. peripheral circuit of pins 0v vss (def) 41 power source for deflection block. vdd (def) 42 power source for deflection block. 5.0v 5% y c a fbp in 43 y c a h out 44 cmos in/out 1 impedance>100k (input) impedance<100 (output) cmos in/out 1 impedance>100k (input) impedance<100 (output) 43 44 v ol : 0v v oh : 5v y s c a 45 cmos in/out 2 impedance>100k (input) impedance<100 (output) sda 45 v il = 0v : rgb output v ih = 5v : blanking v il : 0v v ih : 5v name note
mi tsub ishi M65580MAP-XXXFP mitsubishi semiconductor < digital ic > digital video/chroma/deflection + mcu preliminary note : this is not a final specification. some of information in this document are subject to changes. 2 5 pin no. peripheral circuit of pins y c a y s cmos schmitt in y c a cmos in/out 1 impedance>100k (input) impedance<100 (output) cmos in/out 1 impedance>100k (input) impedance<100 (output) 46 47 osd(g) in 49 osd(b) in 48 osd(r) in 51 48 49 51 half tone in 47 scl 46 y c a cmos in/out 1 fast blk in 50 impedance>100k (input) impedance<100 (output) 50 rgb output half tone on v il : 0v v ih : 5v v il = 0v : v ih = 5v : v il : 0v v ih : 5v v il = 0v : rgb output v ih = 5v : osd output impedance>100k name note
mi tsub ishi M65580MAP-XXXFP mitsubishi semiconductor < digital ic > digital video/chroma/deflection + mcu preliminary note : this is not a final specification. some of information in this document are subject to changes. 2 6 pin no. peripheral circuit of pins v sync out 52 h sync out 53 y c a y c a 52 53 y 54 p5 1 /vsync 54 cmos input impedance>100k y c a cmos in/out 1 impedance>100k (input) impedance<100 (output) p5 2 /r 55 p5 3 /out1 56 p3 0 /g 57 p3 1 /b 58 p1 0 /out2 59 v ol : 0v v oh : 5v cmos in/out 1 impedance>100k (input) impedance<100 (output) cmos in/out 1 impedance>100k (input) impedance<100 (output) v ol : 0v v oh : 5v name note
mi tsub ishi M65580MAP-XXXFP mitsubishi semiconductor < digital ic > digital video/chroma/deflection + mcu preliminary note : this is not a final specification. some of information in this document are subject to changes. 2 7 pin no. peripheral circuit of pins y c a p1 1 /scl1 60 p1 2 /scl2 61 p1 3 /sda1 62 p1 4 /sda2 63 cmos in/out 1 impedance>100k (input) impedance 250 (output) y p0 0 /pwm0 64 p0 1 /pwm1 65 p0 2 /pwm2 66 p0 3 /pwm3 67 cmos in/out impedance>100k (input) impedance 250 (output) p0 4 /pwm4 68 y p0 5 /ad3 69 p0 6 /int2/ad4 70 cmos in/out impedance>100k (input) impedance 250 (output) y p0 7 /int1 71 cmos in/out impedance>100k (input) impedance 250 (output) 71 name note
mi tsub ishi M65580MAP-XXXFP mitsubishi semiconductor < digital ic > digital video/chroma/deflection + mcu preliminary note : this is not a final specification. some of information in this document are subject to changes. 2 8 pin no. peripheral circuit of pins y c a cmos in/out 1 impedance>100k (input) impedance<100 (output) p2 3 /tim3 72 p2 4 /tim2 73 y c a p2 5 /ad5 74 cmos in/out 1 impedance>100k (input) impedance 250 (output) 74 75 hlf 75 76 vhold 76 cv in 77 77 impedance=n.a. (additional filter on pcb board) name note
mi tsub ishi M65580MAP-XXXFP mitsubishi semiconductor < digital ic > digital video/chroma/deflection + mcu preliminary note : this is not a final specification. some of information in this document are subject to changes. 2 9 pin no. peripheral circuit of pins cn vss 78 cmos in/out impedance>100k (input) impedance 250 (output) 78 79 80 x in 79 x out 80 name note
mi tsub ishi M65580MAP-XXXFP mitsubishi semiconductor < digital ic > digital video/chroma/deflection + mcu preliminary note : this is not a final specification. some of information in this document are subject to changes. 30 memory map 0000 16 00c0 16 00ff 16 087f 16 sfr1 area ffff 16 0800 16 interrupt vector area special page osd ram (128 bytes) (note) zero page 0200 16 020f 16 sfr2 area not used 0300 16 00bf 16 0100 16 01ff 16 05bf 16 6000 16 rom (40k bytes) 10000 16 1ffff 16 rom correction function vector 1: addresses 0300 16 vector 2: addresses 0320 16 0320 16 ff00 16 ffde 16 11400 16 13bff 16 osd rom (10k bytes) not used mask rom version ram (1152 bytes) not used not used not used not used

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